Semiconductor integrated circuit device having compensation for wiring distance delays

ABSTRACT

A third gate circuit which is controlled by a clock signal and operates upon the detection of change of a signal on a critical path driven by a first gate circuit and transmits a signal provided by the first gate circuit to a second gate circuit is connected to the critical path at a position near the second gate circuit. The third gate circuits operates upon the detection of change of the signal to increase the speed of change of the signal. Thus, the ratio of a delay time attributable to wiring resistance in the critical path of a semiconductor integrated circuit is reduced, the speed of the critical path is increased and the operating frequency of the semiconductor integrated circuit can be improved.

TECHNICAL FIELD

The present invention relates to a semiconductor integrated circuitdevice having a large chip size that is provided with miniaturizedwiring lines and more particularly, to a circuit configuration suitablefor reducing wiring delay.

BACKGROUND ART

Conventional methods of increasing the speed of critical paths in asemiconductor integrated circuit include (A) reducing the basic delaytime of gate circuits, (B) increasing the load driving force of gatecircuits and (C) distributing output load by multiplexing gate circuits.

A precharge circuit is effective in the methods (A) and (B). An outputnode in a precharge circuit is precharged, and the precharge circuit isdriven by a transistor having a low output impedance.

Although these speed increasing methods are effective on capacity load,the effect of these speed increasing methods are not as effective asexpected on resistance load, such as the resistance of wiring lines.

In a conventional semiconductor integrated circuit, wiring resistance islow as compared with the on-resistance of a load driving transistor ofthe gate circuit. Therefore, the speed of the critical path can beincreased by the speed increasing method effective in capacity load.

However, since the semiconductor integrated circuit has some long wiringlines, the necessity of increasing the speed of the long wiring lineshas been understood. It has been proposed to increase the speed of longwiring lines by providing the long wiring lines with a relay buffer asmentioned in JP-A No. Hei 4-23347. The foregoing method of increasingthe speed is effective when the ratio of wiring delay in the criticalpath is small as compared with a delay time taken by the gate circuit.However, the effect of the increase of speed decreases when the ratio ofwiring delay is increased due to the enlargement of the semiconductorintegrated circuit and the miniaturization of the wiring lines.

It is mentioned in connection with the effect of wiring delay in “Designof high-speed LSI”, Nikkei Electronics, No. 13, pp. 177-183, SpecialEdition, (March, 1995) that the ratio of wiring delay increases beyond50% when the operating frequency exceeds 100 MHz and design rules are0.35 μm.

Problems relating to wiring delay are contradictory to theminiaturization of semiconductor integrated circuits and the importancethereof will progressively increase in the future. At the present, thereduction of wiring delay, similarly to the increase of the speed ofgate circuits, is an important problem in increasing the speed ofcritical paths.

A conventional method which inserts a relay buffer into a long wiringline needs inverters arranged in two stages to match the polarities ofsignals and is not effectively applicable to all cases for speedincrease.

Accordingly, it is an object of the present invention to reduce theratio of delay time caused by wiring resistance in a critical pathincluded in a semiconductor integrated circuit, to increase the speed ofthe critical path and to improve the operating frequency of thesemiconductor integrated circuit. Another object of the presentinvention is to increase long wiring driving speed, the distribution ofnoise sources by distributing long wiring line driving circuits, and toprevent the reduction of reliability due to electromigration.

DISCLOSURE OF THE INVENTION

According to the present invention, a semiconductor integrated circuitdevice comprises a first gate circuit, and a second gate circuit thatreceives an output signal provided by the first gate circuit andprovides a signal to the following circuit, wherein a third gate circuitfor increasing the changing speed of the output signal of the first gatecircuits connected to a wiring line interconnecting the first and thesecond gate circuits at a position near the second gate circuit.

In this semiconductor integrated circuit device, the ratio of wiringdelay due to wiring resistance in a critical path included in thesemiconductor integrated circuit device is reduced and, consequently,the speed of the critical path can be increased and the operatingfrequency of the semiconductor integrated circuit can be improved.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram of a semiconductor integrated circuit devicein a first embodiment according to the present invention;

FIG. 2 is a circuit diagram of a semiconductor integrated circuit devicein a second embodiment according to the present invention;

FIG. 3 is a circuit diagram of a semiconductor integrated circuit devicein a third embodiment according to the present invention;

FIG. 4 is a circuit diagram of a semiconductor integrated circuit devicein a fourth embodiment according to the present invention;

FIG. 5 is a circuit diagram of a semiconductor integrated circuit devicein a fifth embodiment according to the present invention;

FIG. 6 is a circuit diagram of a semiconductor integrated circuit devicein a sixth embodiment according to the present invention;

FIG. 7 is a circuit diagram of a semiconductor integrated circuit devicein a seventh embodiment according to the present invention; and

FIG. 8 is a time chart of assistance in explaining the operation of thesemiconductor integrated circuit device in the third embodiment shown inFIG. 3.

BEST MODE FOR CARRYING OUT THE INVENTION

Preferred embodiments of the present invention will be described withreference to the accompanying drawings, in which like or correspondingparts are designated by the same reference characters.

FIG. 1 shows a first embodiment of the present invention. Shown in FIG.1 are a clock signal CK, a precharge circuit 100, a gate circuit 200, aspeed increasing circuit 300, and a long line 400.

The precharge circuit 100 comprises a power supply terminal 101, aPMOSFET 102, a logic circuit 103 comprising NMOSFETs, an NMOSFET 104 anda grounding terminal 105. While the clock signal CK is LOW, the PMOSFET102 is closed and the output 108 of the precharge circuit 100 isprecharged to HIGH. While the clock signal CK is HIGH, NMOSFETs areclosed and the NMOS logic circuit 103 receives input signals 106 to 107and operates to maintain an output signal 108 HIGH or at a groundpotential.

The speed increasing circuit 300 comprises a power supply terminal 101,a PMOSFET 301, NMOSFETs 302, 303 and 304, and a grounding terminal 105.While the clock signal CK is LOW, the NMOSFET 303 is open and a signal305 is on a level equal to that of an output signal provided by theprecharge circuit 100. While the clock signal CK is HIGH, the output ofan inverter formed of the PMOSFET 301 and the NMOSFET 302 goes LOW ifthe signal 305 is HIGH, and the output signal of the precharge circuit100 is transferred directly to the signal 305. When the clock signal CKis HIGH and the signal 305 is LOW, an output of an inverter formed ofthe PMOSFET 301 and the NMOSFET 302 goes HIGH and, consequently, theNMOSFETs 303 and 304 close simultaneously to make the signal 305 go LOW.

While the clock signal CK is LOW, the output 109 of the prechargecircuit 100 remains HIGH, and the output signal 108 of the prechargecircuit 100 is transferred through the line 400 to the signal 305. Thespeed increasing circuit 300 does not affect the signal 305 because theNMOSFET 303 is open. The NMOSFET 303 remains open to avoid conflictbetween the precharge circuit 100 and the speed increasing circuit 300in a precharging period in which the precharge circuit 1100 executes aprecharging operation, i.e., in which the signal 305 changes from LOW toHIGH.

While the clock signal CK is HIGH, the output signal 108 of theprecharge circuit 100 varies according to the input signals 106 to 107.Suppose that the level of the output signal 108 is changed to LOW. Then,the change of the output signal 108 is transferred through the line 400to the signal 305. When the output signal 305 starts changing from HIGHto LOW, the output of the inverter formed of the PMOSFET 301 and theNMOSFET 302 of the speed increasing circuit 300 changes from LOW to HIGHand, consequently, both the NMOSFETs 303 and 304 close to change thelevel of the signal 305 quickly to LOW.

The reaction speed of the speed increasing circuit 300 is greatlydependent on the logical threshold of the inverter formed of the PMOSFET301 and the NMOSFET 302. The reaction speed is high when the logicalthreshold is high. Practically, it is preferable that the logicalthreshold is raised to an extent which will not be affected by noisegenerated by a power supply and the signal line 305.

In this embodiment, when the driving circuit comprising the prechargecircuit, and the next gate circuit are separated by a distance exceedinga fixed distance, the precharge circuit is able to achieve an operationto change to LOW at a high speed when the speed increasing circuit isdisposed near the next gate circuit.

When the precharge circuit needs to drive a large capacity load, noisesources can be dispersed and the design of power lines subject torestrictions by electromigration can be facilitated because drivers canbe distributed (the speed increasing circuit takes part of the loaddriving).

FIG. 2 shows a second embodiment of the present invention. The secondembodiment differs from the first embodiment shown in FIG. 1 only in theconfiguration of a speed increasing circuit 500. The speed increasingcircuit 500 comprises a PMOSFET 501 and NMOSFETs 502, 503 and 504. ThePMOSFET 501 and the NMOSFET 502 form an inverter, and the NMOSFETs 502and 504 are connected so as to form a current mirror circuit.

The embodiment shown in FIG. 2 is the same in function and effects asthe first embodiment shown in FIG. 1.

FIG. 3 shows a third embodiment of the present invention. In FIG. 3,indicated at 600 is a precharge circuit. The precharge circuit 600 isconstructed by additionally connecting an inverter 601 to the output ofthe precharge circuit 100 shown in FIG. 1. Therefore, an output signal602 is LOW during a precharging period in which the clock signal CK isLOW.

An inverter 700 supplies an inverted signal obtained by inverting theclock signal CK to a speed increasing circuit 800. The speed increasingcircuit 800 differs from the speed increasing circuit 300 shown in FIG.1 in that an output of an inverter formed of a PMOSFET 301 and anNMOSFET 302 is applied to a PMOSFET 801, and a PMOSFET 802 having a gatecontrolled by the inverter 700 is interposed between the PMOSFET 801 anda signal 803.

In the third embodiment shown in FIG. 3, the speed of change from LOW toHIGH of an output signal 602 of the precharge circuit 600 and the signal803 on a line 400 can be increased. FIG. 8 is a time chart of assistancein explaining the operation of the semiconductor integrated circuitdevice shown in FIG. 3.

The third embodiment is the same in effect in distributing noise sourcesand electromigration as the first embodiment shown in FIG. 1.

FIG. 4 shows a fourth embodiment. The fourth embodiment differs from thethird embodiment shown in FIG. 3 in the configuration of a speedincreasing circuit 900. The speed increasing circuit 900 comprisesPMOSFETs 901, 903 and 904, and an NMOSFET 902. The PMOSFET 901 and theNMOSFET 902 form an inverter, and the PMOSFETs 901 and 903 are connectedso as to form a current mirror circuit.

The fourth embodiment shown in FIG. 4 is the same in function and effectas the third embodiment shown in FIG. 3.

FIG. 5 shows a fifth embodiment of the present invention. In FIG. 5,indicated at 1000 is a driving circuit comprising a precharge circuit ora static circuit, and at 1100 is a speed increasing circuit. The speedincreasing circuit 1100 comprises a delay circuit 1101, PMOSFETs 1102,1104 and 1105, and NMOSFETs 1103, 1106 and 1107. An output provided byan inverter formed of the PMOSFET 1102 and the NMOSFET 1103 is given tothe PMOSFET 1104 and the NMOSFET 1107. The PMOSFETs 1104 and 1105increases the speed of change of a signal 1108 from LOW to HIGH. TheNMOSFETs 1106 and 1107 increases the speed of change of the signal 1108from HIGH to LOW.

The delay circuit 1101 executes an operation to prevent conflict betweenthe driving circuit 1000 and the speed increasing circuit 1100. Thefunctions of the delay circuit 1101 are the same as those of the clocksignals CK used in the semiconductor integrated circuit devices shown inFIGS. 1 to 4.

Suppose that the signal 1108 and the output of the delay circuit 1101are LOW. When the signal 1108 changes from LOW to HIGH, the PMOSFETs1104 and 1105 make the signal 1108 go HIGH at a high speed. Since theoutput signal of the delay circuit 1101 goes HIGH after the elapse of afixed time, the PMOSFET 1105 opens to stop the function of the speedincreasing circuit 1100. The output signal of the delay circuit 1101 isLOW in a period in which the signal 1108 changes from LOW to HIGH.Therefore, any current does not flow through the NMOSFETs 1106 and 1107.

When the signal 1108 changes from HIGH to LOW, the inverter formed ofthe PMOSFET 1102 and the NMOSFET 1103 reacts to the change of the signal1108 because the PMOSFET 1105 is open and the NMOSFET 1106 is closed.When the output signal of the inverter starts changing to HIGH, thesignal 1108 is changed quickly to LOW through the NMOSFETs 1106 and1107.

In this embodiment, the control signal of the speed increasing circuit1100 is self-generated by the delay circuit 1101. The speed increasingcircuit may be controlled by a clock signal generated by shifting thephase of the clock signal for controlling the driver.

The fifth embodiment is capable of increasing the speed of signal changeeven if the driving circuit is either a precharge circuit or a staticcircuit. The fifth embodiment is capable of quickly achieving both thechange of the signal from LOW to HIGH and the change of the same fromHIGH to LOW.

The effect of the fifth embodiment in distributing noise sources andelectromigration is the same as that of the first embodiment shown inFIG. 1.

FIG. 6 shows a sixth embodiment of the present invention. The sixthembodiment is an application of the present invention to a deviceprovided with a plurality of following gates 200 connected in series. InFIG. 6, indicated at 1200 land 1300 are speed increasing circuitssimilar to the foregoing speed increasing circuits. The sixth embodimentis characterized by the plurality of speed increasing circuits connectedto lines connecting a driving circuit 100 to the following gatecircuits. Thus, a signal can be transferred from the driving circuit 100to the following gate circuit 200 at a further increased speed.

The sixth embodiment is shown in a configuration for achieving a changeto LOW at a high speed. The driving circuit and the speed increasingcircuit may properly be combined to achieve a change to HIGH at a highspeed or to achieve changes from LOW to HIGH and vice versa.

FIG. 7 shows seventh embodiment of the present invention, In FIG. 7,indicated at 1400 is a semiconductor integrated circuit device, and at1401 to 1404 are logical blocks. Driving circuits 1410 to 1412 drive asignal line 1430. The driving circuits 1410 to 1412 are controlled by aclock signal supplied to a semiconductor integrated circuit. In FIG. 7,indicated at d1413 to 1415 are following gate circuits and at 1420 to1422 are speed increasing circuits in accordance with the presentinvention.

The seventh embodiment has the signal line 1430 extended all over thesemiconductor integrated circuit, and is provided with the plurality ofdriving circuits for driving the signal line 1430, and the plurality offollowing gate circuits. Therefore, high-speed signal transfer can beachieved by connecting the plurality of speed increasing circuits to thesignal line 1430.

The seventh embodiment is capable of increasing signal transfer speedmore effectively than a device in which an intermediate buffer isconnected to the signal line 1430, and of increasing signal transferspeed regardless of the polarity, i.e., positive polarity or negativepolarity, of the signal line.

CAPABILITY OF EXPLOITATION IN INDUSTRY

As apparent from the foregoing description, the present invention issuitable for application to a semiconductor integrated circuit devicehaving a large chip size and provided with miniaturized wiring lines.

What is claimed is:
 1. A semiconductor integrated circuit devicecomprising: a first driving circuit comprising a precharge circuit thatis controlled by a first clock signal; a next gate circuit that receivesan output signal provided by the first driving circuit through atransmission line; and a speed increasing circuit that is controlled bya second clock signal, that detects the change of the output signal ofthe first driving circuit, that increases the speed of changing theoutput signal of the first driving circuit and that is connected to thetransmission line connecting the next gate circuit to the first drivingcircuit at a connecting position of the transmission line, wherein aline length between the connecting point and the next gate circuit isshorter than a line length between the connecting point and the firstdriving circuit, and wherein the output signal of the first drivingcircuit varies according to input signals of the first driving circuit.2. The semiconductor integrated circuit device according to claim 1,wherein the first driving circuit is precharged in a period while thefirst clock signal is LOW or HIGH and becomes operative in a period inwhich the first clock signal is HIGH or LOW.
 3. The semiconductorintegrated circuit device according to claim 1, wherein the second clocksignal is supplied from the first clock signal.
 4. The semiconductorintegrated circuit device according to claim 1, further including aplurality of the next gate circuits that are connected to thetransmission line connected to the first driving circuit, and aplurality of speed increasing circuits being connected to thetransmission line at connecting points of the transmission line inaccordance with the plurality of next gate circuits.
 5. Thesemiconductor integrated circuit device according to claim 1, furtherincluding a plurality of the driving circuits that are controlled by thefirst clock signal and drive the transmission line.
 6. The semiconductorintegrated circuit device according to claim 1, wherein the speedincreasing circuit operates to increase the speed of change of thetransmission line connecting the first circuit to the next gate circuitfrom LOW to HIGH or from HIGH to LOW.
 7. The semiconductor integratedcircuit device according to claim 2, wherein each of the first and thesecond clock signals is supplied from clock signals of the same phase inthe semiconductor integrated circuit device.
 8. The semiconductorintegrated circuit device according to claim 2, further including aplurality of next gate circuits that are connected to the transmissionline connected to the first driving circuit, and a plurality of speedincreasing circuits is connected to the transmission line at connectingpositions of the transmission line in accordance with the plurality ofnext gate circuits.
 9. The semiconductor integrated circuit deviceaccording to claim 3, further including a plurality of next gatecircuits that are connected to the transmission line connected to thefirst driving circuit, and a plurality of speed increasing circuits isconnected to the transmission line at connecting positions of thetransmission line in accordance with the plurality of next gatecircuits.
 10. The semiconductor integrated circuit device according toclaim 2, further including a plurality of the driving circuits that arecontrolled by the first clock signal and drive the transmission line.11. The semiconductor integrated circuit device according to claim 3,further including a plurality of the driving circuits that arecontrolled by the first clock signal and drive the transmission line.12. The semiconductor integrated circuit device according to claim 4,further including a plurality of the driving circuits that arecontrolled by the first clock signal and drive the transmission line.13. The semiconductor integrated circuit device according to claim 2,wherein the speed increasing circuit operates to increase the speed ofchange of the transmission line connecting the first circuit to the nextgate circuit from LOW to HIGH or from HIGH to LOW.
 14. The semiconductorintegrated circuit device according to claim 3, wherein the speedincreasing circuit operates to increase the speed of change of thetransmission line connecting the first circuit to the next gate circuitfrom LOW to HIGH or from HIGH to LOW.
 15. The semiconductor integratedcircuit device according to claim 4, wherein the speed increasingcircuit operates to increase the speed of change of the transmissionline connecting the first circuit to the next gate circuit from LOW toHIGH or from HIGH to LOW.
 16. The semiconductor integrated circuitdevice according to claim 5, wherein the speed increasing circuitoperates to increase the speed of change of the transmission lineconnecting the first circuit to the next gate circuit from LOW to HIGHor from HIGH to LOW.